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Triple 8-Bit Analog-to-Digital-Converter
SDA 9205-2
Preliminary Data Features Three equivalent CMOS A/D converters on chip 30-MHz sample rate 8-bit resolution No external sample & hold required On-chip input buffer for each analog channel Internal clamping circuits for each of the ADCs Different digital output multiplex formats: - 3 independent unmultiplexed 8-bit outputs - Multiplexed formats compatible to inputs of all Siemens Featureboxes and Siemens TV-SAM - CCIR 656 output format q Overflow and underflow outputs
q q q q q q q
CMOS IC
P-LCC-68-1
Type SDA 9205-2 General Description
Ordering Code Q67100-H5069
Package P-LCC-68-1 (SMD)
The SDA 9205-2 is a single monolithic IC containing three separate 8-bit analog to digital converters for video (YUV) applications. It utilizes an advanced VLSI 1.2 m CMOS process providing 30-MHz sampling rates at 8 bits. Different digital output multiplex formats are selectable on chip via several control inputs, compatible to inputs of all Siemens Featureboxes, Siemens TV-SAM, and CCIR 656 output format. The ADCs have no missing codes over the full operating temperature range of 0 to + 70 C. Operation is from + 5 V DC-power supply.
Semiconductor Group
1
01.94
SDA 9205-2
Pin Configuration (top view)
Semiconductor Group
2
SDA 9205-2
Pin Definitions and Functions Pin No. 63 to 2 3 4 5 6 7 8/9/11/17 10 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27/29 28 30 31 32 33 34 to 41 42 43 Symbol C7 to C0 Function Digital outputs of ADC C (port C) C0 least significant bit Output stages supply ground of port C Underflow data output of ADC C Overflow data output of ADC C Output enable of port C Binary/two's complement output port C Control inputs for different digital output multiplex formats - refer to logic table Reference voltage high of ADC C (+ 2.5 V) Analog positive supply voltage of ADC C (+5 V) Analog ground of ADC C Reference voltage low of ADC C (+ 5 V) Analog voltage input of ADC C Reference voltage high of ADC B (+ 2.5 V) Analog positive supply voltage of ADC B (+ 5 V) Analog ground of ADC B Reference voltage low of ADC B (+ 0.5 V) Analog voltage input of ADC B Reference voltage high of ADC A (+ 2.5 V) Analog positive supply voltage of ADC A (+ 5 V) Analog ground of ADC A Analog voltage input of ADC A Reference voltage low of ADC A (+ 0.5 V) Factory use only, connect to 0 V Binary/two's complement output of port A Clamp input for all three channels Underflow data output of ADC A Overflow data output of ADC A Output stages supply ground of port A Digital outputs of ADC A (port A) A0 least significant bit Output enable of port A Output stages supply voltage of port A
VQGNDC
UFLC OFLC OENC DTC CONT3CONT0
VREFHC VCCC VAGNDC VREFLC
AINC
VREFHB VCCB VAGNDB VREFLB
AINB
VREFHA VCCA VAGNDA
AINA
VREFLA
TEST DTA CLAMP UFLA OFLA
VQGNDA
A7 to A0 OENA
VDDQA
Semiconductor Group
3
SDA 9205-2
Pin Definitions and Functions (cont'd) Pin No. 44 45 46 47 48 to 55 56 57 58 59 60 61 62 Symbol OENB UFLB OFLB Function Output enable of port B Underflow data output of ADC B Overflow data output of ADC B Output stages supply ground of port B Digital outputs of ADC B (port B) B0 least significant bit Output stages supply voltage of port B Clock input Digital ground Format sync input Binary/two's complement output of port B Digital positive supply voltage (+ 5 V) Output stages supply voltage of port C
VQGNDB
B7 to B0
VDDQB
CLK
VDGND
FSY DTB
VDD VDDQC
Semiconductor Group
4
SDA 9205-2
Circuit Description Analog to Digital Converter The SDA 9205-2 implements 3 independent 8-bit analog-to-digital converters. They are two step converters with a coarse comparator block and two fine comparator blocks each using pipeline architecture for high speed sampling performance. During the first clock cycle, the coarse comparator samples and determines 4 MSBs and one of the fine comparator blocks samples the input voltage. During the second clock cycle this fine comparator block makes its decision for the 4 LSBs. So the coarse comparator block makes its decisions at each clock cycle, the fine comparator blocks make the comparison alternating every two clock cycles. The converter uses the redundancy principle to correct fine conversion. The sample and hold function has been distributed in each comparator due to the two step conversion principle. Clamping An internal clamping circuit is provided in each of three analog channels. The analog pins AINA, AINB, AINC are switched simultaneously to on chip generated clamping levels by an active high pulse on pin 30 (CLAMP).
Clamping Levels Analog Channel AINA AINB, AINC Dual Code 00010000 10000000 Components (Y) (U, V)
Semiconductor Group
5
SDA 9205-2
The external clamping capacitance is loaded by on chip current sources (typ. 200 A) during clamping. So the loading time depends on the values of Cext cl. The loading time for a complete loading cycle is 1200 CLK pulses typical (44 s with 27 MHz CLK and Cext cl = 10 nF) as shown in figure 1.
Cext cl = 10 nF, RS = 50
Figure 1 Typical Clamp Timing Diagram
Semiconductor Group
6
SDA 9205-2
Digital Signal Processing The digital signal processing block performs averaging of sampled data. The , , 8-bit busses represent the results of DSP function with input data from a, b, c, 8-bit busses. A special DSP function in combination with a special output coding format is defined by four control pins CONT0 ... CONT3 (see Output Coding).
Figure 2 Interfaces of ADC-, DSP- and Output Coding Block
Semiconductor Group
7
SDA 9205-2
The following DSP functions are available (1.0) (1.1) (2.0) (2.1) (2.2) (2.3) n = an - 3 n = 1/2 (an - 4 + an - 3) n = bn - 3 n = 1/2 (bn - 4 + bn - 3) 4n = 1/4 (b4n - 5 + b4n - 4 + b4n - 3 + b4n - 2n), 4n - 3,2,1 8n = 1/8 (b8n - 7 + b8n - 6 + ..... + b8n), 8n - 7,6,5,4,3,2,1 arbitrarily arbitrarily n = sampling point ADC B ADC A
(2.0) (2.1) (2.2) (2.3)
n = c n - 3 n = 1/2 (cn - 4 + cn - 3) 4n = 1/4 (c4n - 5 + c4n - 4 + c4n - 3 + c4n - 2) 8n = 1/8 (c8n - 7 + c8n - 6 + ..... + c8n) 4n - 3,2,1 8n - 7,6,5,4,3,2,1 arbitrarily arbitrarily
ADC C
Averaged results are rounded to eight bits (X 0.5 0; X > 0.5 1) A group delay of 0.5 CLK cycles exists between DSP (1.0, 2.0) and the other DSP functions.
Semiconductor Group
8
SDA 9205-2
Figure 3 DSP Function Detailed function of DSP block is shown in figure 3.
Semiconductor Group
9
SDA 9205-2
Output Coding Eight different digital output multiplex formats are available. They are selectable via four control lines CONT0 ... CONT3. These multiplexed formats perform combinations of DSP functions of the several converters (A, B, C). DSP functions - output coding combinations Format 8:8:8 DSP 1.0 + 2.0 1.1 + 2.1 1.0 + 2.0 1.1 + 2.1 1.0 + 2.0 1.1 + 2.2 1.0 + 2.0 1.1 + 2.3 1.0 + 2.0 1.1 + 2.1 1.0 + 2.0 1.1 + 2.1 1.0 + 2.0 1.1 + 2.2 1.0 + 2.0 1.1 + 2.3 CONT3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CONT2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CONT1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CONT0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
8:4:4
8:2:2
8:1:1
4:8:8
4:4:4
4:2:2
4:1:1
Semiconductor Group
10
SDA 9205-2
The digital output data are synchronized by the FSY signal. The first high of FSY defines the first output format byte and is synchronized to CLK. In case of asynchronism the first (in formats 8:1:1, 4:1:1 the first and the second) output format byte after FSY had gone high does not contain valid data. Timing of FSY, CLK and output data is shown in figure 4 with output format 4:1:1.
Figure 4
Semiconductor Group
11
SDA 9205-2
Format 8:8:8 DSP Function CONT3 1.0 + 2.0 1.1 + 2.1 0 0 0 0 Coding CONT2 CONT1 0 0 CONT0 0 1 DSP bus 7 0 time index bit number
Port
Bit A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0
Data 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 n 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 n+1 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 n+2 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 3 n+3 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 n+4 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 5 n+5 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 n+6 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 7 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 7 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 7 n+7
A
B
C
Time Index
Semiconductor Group
12
SDA 9205-2
Format 8:4:4 DSP Function CONT3 1.0 + 2.0 1.1 + 2.1 0 0 0 0 Coding CONT2 CONT1 1 1 CONT0 0 1 DSP bus 7 0 time index bit number
Port
Bit A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0
Data 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 T T T T T T T T n 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 T T T T T T T T n+1 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 T T T T T T T T n+2 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 3 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 T T T T T T T T n+3 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 T T T T T T T T n+4 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 5 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 T T T T T T T T n+5 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 T T T T T T T T n+6 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 7 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 T T T T T T T T* n+7
A
B
C
Time Index
* T ... Tristate
Semiconductor Group
13
SDA 9205-2
Format 8:2:2 DSP Function CONT3 1.0 + 2.0 1.1 + 2.2 0 0 1 1 Coding CONT2 CONT1 0 0 CONT0 0 1 DSP bus 7 0 time index bit number
Port
Bit A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0
Data 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 7 0 6 0 T T T T T T T T T T T T n 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 5 0 4 0 5 0 4 0 T T T T T T T T T T T T n+1 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 3 0 2 0 3 0 2 0 T T T T T T T T T T T T n+2 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 3 1 0 0 0 1 0 0 0 T T T T T T T T T T T T n+3 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 4 6 4 7 4 6 4 T T T T T T T T T T T T n+4 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 5 5 4 4 4 5 4 4 4 T T T T T T T T T T T T n+5 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 3 4 2 4 3 4 2 4 T T T T T T T T T T T T n+6 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 7 1 4 0 4 1 4 0 4 T T T T T T T T T T T T* n+7
A
B
C
Time Index
* T ... Tristate
Semiconductor Group
14
SDA 9205-2
Format 8:1:1 DSP Function CONT3 1.0 + 2.0 1.1 + 2.3 0 0 1 1 Coding CONT2 CONT1 1 1 CONT0 0 1 DSP bus 7 0 time index bit number
Port
Bit A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0
Data 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 7 0 6 0 T T T T T T T T T T T T n 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 7 0 6 0 7 0 6 0 T T T T T T T T T T T T n+1 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 5 0 4 0 5 0 4 0 T T T T T T T T T T T T n+2 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 3 5 0 4 0 5 0 4 0 T T T T T T T T T T T T n+3 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 3 0 2 0 3 0 2 0 T T T T T T T T T T T T n+4 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 5 3 0 2 0 3 0 2 0 T T T T T T T T T T T T n+5 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 1 0 0 0 1 0 0 0 T T T T T T T T T T T T n+6 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 7 1 0 0 0 1 0 0 0 T T T T T T T T T T T T* n+7
A
B
C
Time Index
* T ... Tristate
Semiconductor Group
15
SDA 9205-2
Format 4:8:8 DSP Function CONT3 1.0 + 2.0 1.1 + 2.1 1 1 0 0 Coding CONT2 CONT1 0 0 CONT0 0 1 DSP bus 7 0 time index bit number
Port
Bit A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0
Data 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 n 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 n+1 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 n+2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 3 n+3 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 n+4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 5 n+5 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 n+6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 7 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 7 n+7
A
B
C
Time Index
Semiconductor Group
16
SDA 9205-2
Format 4:4:4 DSP Function CONT3 1.0 + 2.0 1.1 + 2.1 1 1 0 0 Coding CONT2 CONT1 1 1 CONT0 0 1 DSP bus 7 0 time index bit number
Port
Bit A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0
Data 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 n 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 n+1 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 n+2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 n+3 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 n+4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 n+5 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 n+6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 n+7
A
B
C
Time Index
Semiconductor Group
17
SDA 9205-2
Format 4:2:2 DSP Function CONT3 1.0 + 2.0 1.1 + 2.2 1 1 1 1 Coding CONT2 CONT1 0 0 CONT0 0 1 DSP bus 7 0 time index bit number
Port
Bit A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0
Data 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 n 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 n+1 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 n+2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 n+3 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 n+4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 n+5 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 n+6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 n+7
A
B
C
Time Index
Semiconductor Group
18
SDA 9205-2
Format 4:1:1 DSP Function CONT3 1.0 + 2.0 1.1 + 2.3 1 1 1 1 Coding CONT2 CONT1 1 1 CONT0 0 1 DSP bus 7 0 time index bit number
Port
Bit A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0
Data 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 7 0 6 0 T T T T T T T T T T T T n 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 0 6 0 7 0 6 0 T T T T T T T T T T T T n+1 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 5 0 4 0 5 0 4 0 T T T T T T T T T T T T n+2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 5 0 4 0 5 0 4 0 T T T T T T T T T T T T n+3 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 3 0 2 0 3 0 2 0 T T T T T T T T T T T T n+4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 3 0 2 0 3 0 2 0 T T T T T T T T T T T T n+5 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 1 0 0 0 1 0 0 0 T T T T T T T T T T T T n+6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 6 1 0 0 0 1 0 0 0 T T T T T T T T T T T T* n+7
A
B
C
Time Index
* T ... Tristate
Semiconductor Group
19
SDA 9205-2
Output Coding for Binary/Two's Complement Mode Binary or two's complement output coding is selectable for each separate output port (A, B, C) via control inputs DTA, DTB, DTC. This coding is independent from selected formats (8:8:8, 8:4:4, 8:2:2, 8:1:1, 4:8:8, 4:4:4, 4:2:2, 4:1:1).
Table 1 Output Coding for Formats 8:8:8, 8:4:4, 8:2:2, 8:1:1, 4:8:8, 4:4:4, 4:2:2, 4:1:1 Table 1 is valid for VREFL = 0.5 V and VREFH = 2.5 V Step VIN Converter A < VCA - 0.125 V VCA - 0.125 V VCA - 0.117 V . . . . VCA + 1.867 V VCA + 1.875 V > VCA + 1.875 V VIN Converter B, C < VCB, C - 1 V VCB, C - 1 V VCB, C - 0.992 V . . . . VCB, C + 0.992 V VCB, C + 1 V > VCB, C + 1 V OFL UFL Binary Bit Bit Output 76543210 0 0 0 . . . . . 0 1 1 0 0 . . . . . 0 0 00000000 00000000 00000001 . . . . 11111110 11111111 11111111 Two's Complement 76543210 10000000 10000000 10000001 . . . . 01111110 01111111 01111111
Underflow 0 1 . . . . 254 255 Overflow
VCA = ext. clamping level during CLAMP high pulse at Cext cl on channel AINA. VCB, C = ext. clamping level during CLAMP high pulse at Cext cl on channel AINB and AINC.
In output format 4:2:2 a special suppression of code 0 and code 255 is provided in the binary output mode.
Semiconductor Group
20
SDA 9205-2
Table 2 Output Coding for Format 4:2:2 Table 2 is valid for VREFL = 0.5 V and VREFH = 2.5 V Step VIN Converter A < VCA - 0.125 V VCA - 0.125 V VCA - 0.117 V . . . . VCA + 1.867 V VCA + 1.875 V > VCA + 1.875 V VIN Converter B, C < VCB, C - 1 V VCB, C - 1 V VCB, C - 0.992 V . . . . VCB, C + 0.992 V VCB, C + 1 V > VCB, C + 1 V OFL UFL Binary Bit Bit Output 76543210 0 0 0 0 . . 0 0 0 1 1 0 0 . . . 0 0 0 0 00000001 00000001 00000001 00000010 . . 11111101 11111110 11111110 11111110 Two's Complement 76543210 10000000 10000000 10000001 10000010
Underflow 0 1 2 . . 253 254 255 Overflow
VCA = ext. clamping level during CLAMP high pulse at Cext cl on channel AINA. VCB, C = ext. clamping level during CLAMP high pulse at Cext cl on channel AINB and AINC.
Semiconductor Group
21
SDA 9205-2
Block Diagram
Absolute Maximum Ratings Parameter Supply voltages1) Input voltage range all inputs Ambient temperature Storage temperature
1)
Symbol min.
Limit Values max. 6.5 - 0.3 0 - 55
Unit V V C C
VCC, VDD VI TA Tstg
VCC + 0.3
70 125
All voltage values are with respect to network ground terminal
Semiconductor Group
22
SDA 9205-2
Characteristics VDD = 5 V 5 %, VCC = 5 V 5 %, VREFH = 2.5 V, VREFL = 0.5 V, VGND = 0 V fCLK = 27 MHz, all specifications min (TA) to max (TA) unless otherwise noted Parameter Symbol min. Power Requirements Analog supply voltage Digital supply voltage Output stage supply voltage Analog supply current Digital supply current Output stages supply current Supply voltage differential Supply voltage differential Reference Inputs Reference voltage high Reference voltage low Reference current Reference ladder resistance Analog Inputs Input range Analog input capacitance Required ext clamp capacitance Required signal source resistance Analog input current Limit Values typ. max. Unit Test Condition
VCC VDD VDDQ ICC IDD IDDQ VCC - VDD
4.75 4.75 4.75
5 5 5
5.25 5.25 5.25 160 20 40
V V V mA mA mA V V
Pins 12, 18, 23 Pin 61 Pins 43, 56, 62 Sum of all VCC pins Sum of all VDD pins Sum of all VDDQ pins
- 0.25
0.25 0.25
VDDQ - VDD - 0.25
VREFH VREFL IREF RREF
0.4 0.5 8 250
2.5
V V mA
Pins 10, 16, 22 Pins 14, 20, 26 Pins 10, 16, 22 each
VI CI Cext cl RS IAIN
2 5 10 200 5 100
Vpp pF nF nA
Single-ended, DC-15 MHz AINA, AINB, AINC, each AINA, AINB, AINC, each
AINA, AINB, AINC, each
Semiconductor Group
23
SDA 9205-2
Characteristics (cont'd) VDD = 5 V 5 %, VCC = 5 V 5 %, VREFH = 2.5 V, VREFL = 0.5 V, VGND = 0 V fCLK = 27 MHz, all specifications min (TA) to max (TA) unless otherwise noted Parameter Symbol min. Digital Inputs L-input voltage H-input voltage Input current Digital Outputs L-output voltage H-output voltage High impedance state output current Performance Sampling rate Full power bandwidth (- 3 dB) Diff. linearity (D.C.) Int. linearity (D.C.) 27 30 MSPS MHz 0.5 0.5 1 1 3 3 3 3 42 46 LSB LSB LSB LSB % degree dB without harmonics 4:1:1 mode DSP 1.0 Limit Values typ. max. Unit Test Condition
VIL VIH II
0 2.0 - 10 5
0.8
VDD
10
V V A
VI = 0 V, VCC
VQL VQH IQZ
0.4 2.4 - 20 20
V V A
ISINK = 1.6 mA ISOURCE = 400 mA VQ = 0 V, VCC
BW DNLE INLE GE DG DP
S/N
10
Clamping level accuracy CLA Gain error Differential gain1) Differential phase1) Signal-to-noise ratio 4.4 MHz sinus Harmonic Distorsion 2./4. order 3. order 5./6. order Supply voltage rejection
1) 2)
fI = 3.6/4.4 MHz
AIN = 1/10 FSR2 )
- 40 - 40 - 46 2.5
dB dB dB %FSR/V2)
4.4 MHz fundamental 4.4 MHz fundamental 4.4 MHz fundamental
Sample test Full scale range (FSR) = 2 V as specified
Semiconductor Group
24
SDA 9205-2
Characteristics (cont'd) VDD = 5 V 5 %, VCC = 5 V 5 %, VREFH = 2.5 V, VREFL = 0.5 V, VGND = 0 V fCLK = 27 MHz, all specifications min (TA) to max (TA) unless otherwise noted Parameter Symbol min. Timing (see figure 5) Output data delay time Output data hold time CLK pulse width CLK rise time CLK fall time Input data setup time Input data hold time Clamp input pulse width Limit Values typ. max. Unit Test Condition
tQD tQH tWH; tWL tTLH tTHL tSU tIH tCi
7 6 10 6 10
25
ns ns ns
CL = 15 pF CL = 15 pF CL = 15 pF CL = 15 pF CL = 15 pF CL = 15 pF CL = 15 pF
1 nF ext. clamp cap.
5 5
ns ns ns ns CLK cycles
Figure 5 Timing Diagram Port A, B, C Semiconductor Group 25
SDA 9205-2
Sample output data-delay is shown on format 8:8:8 with DSP function 1.0 + 2.0
Figure 6 Diagram of Complete Timing There is a delay of 9 clock cycles between sampling of an analog input signal and the corresponding digital output signal.
Semiconductor Group
26
SDA 9205-2
Figure 7 Typ. SNR (without harmonics) versus Analog Frequency (411 Mode DSP 1.0)
References
Figure 8 Blocking the SDA 9205-2
Capacitors: 100 nF - Ceramic 10 nF - Tantal 47 F - Elko
Semiconductor Group
27
SDA 9205-2
VCC
VDD
Grounding
Figure 8 (cont'd) Blocking the SDA 9205-2
Semiconductor Group
28
SDA 9205-2
Chip Capacitors 100 nF (as near as possible to the socket)
Figure 8 (cont'd) Blocking the SDA 9205-2
Semiconductor Group
29
SDA 9205-2
Figure 9 Application Circuit 1 (4:1:1 Format, for Siemens Featurebox) Semiconductor Group 30
SDA 9205-2
Figure 10 Application Circuit 2 (4:1:1 Format, for General Application) Semiconductor Group 31
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